CLK1, CLK0
ADS0
A(12, 13 – 26)
(See Note 1)
SYNCHRONOUS DATA RAM READ CYCLE
tKHKH
tKLKH
tKHKL
tAVKH
tKHAX
A1
tTSVKH
A2
tKHTSX
CWE0 –
CWE7
STANDBY
tEVKH
tKHEX
tWVKH
tKHWX
CNTEN0
CG
DATA OUT
tKHQV
tKHQX1
tGLQV
tGLQX
Q (A1)
tBAVKH
tKHBAX
tGHQZ
tKHQX2
Q (A2)
tKHQV
tKHQZ
Q (A2 + 1)
Q (A2 + 2)
Q (A2 + 3)
READ
BURST READ
NOTES:
1. Cache addresses used are: 13 – 26 for MPC2105A/B; and 12 – 26 for MPC2106A/B.
2. Q1 (A2) represents the first ouput from the external address A2; Q2 (A2) represents the next output data in the burst sequence with
A2 as the base address.
MOTOROLA FAST SRAM
MPC2105A•MPC2106A•MPC2105B•MPC2106B
9