CY7C132(2005) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C132
(Rev.:2005)

2K x 8 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle No. 1 (Either Port-Address Access)[19, 20]

tRC

ADDRESS

tOHA

tAA

DATA OUT PREVIOUS DATA VALID

CY7C132/CY7C136

CY7C142/CY7C146

DATA VALID

Read Cycle No. 2 (Either Port-CE/OE)[19, 21]

CE

OE

tACE

DATA OUT

tLZCE

tLZOE

tDOE

tHZOE

DATA VALID

tPU

ICC

ISB

Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)

ADDRESSR

R/WR

tRC

ADDRESS MATCH

tPWE

DINR

ADDRESSL

BUSYL

DOUTL

tPS

tBLA

Notes:

19. R/W is HIGH for read cycle.

20. Device is continuously selected, CE = VIL and OE = VIL.

21. Address valid prior to or coincident with CE transition LOW.

VALID

ADDRESS MATCH

tBHA

tWDD

tDDD

tHZCE

tPD

tBDD

VALID

Document #: 38-06031 Rev. *C

Page 7 of 18

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