U62H64DK20L Просмотр технического описания (PDF) - Zentrum Mikroelektronik Dresden AG
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U62H64DK20L Datasheet PDF : 8 Pages
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U62H64
Switching Characteristics
Symbol
Alt.
IEC
Time to Output in Low-Z from
E1 LOW or E2 HIGH
G LOW
W HIGH
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LO W to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address Change
E1 HIGH or E2 LOW to Output in
High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
E1 LOW or E2 HIGH to Power-Up
E1 HIGH or E2 LOW to Power-Down
tLZCE
tLZOE
tLZWE
tWC
tRC
tACE
tOE
tAA
tWP
tCW
tAS
tCW
tWP
tDS
tDH
tAH
tOH
tHZCE
tHZWE
tHZOE
tPU
tPD
ten(E)
ten(G)
ten(W)
tcW
tcR
ta(E)
ta(G)
ta(A)
tw(W)
tw(E)
tsu(A)
tsu(E)
tsu(W)
tsu(D)
th(D)
th(A)
tv(A)
tdis(E)
tdis(W)
tdis(G)
Min.
20 25 35
5
5
5
0
0
0
0
0
0
20 25 35
20 25 35
15 15 20
15 20 25
0
0
0
15 20 25
15 15 20
10 10 15
0
0
0
0
0
0
5
5
5
0
0
0
Max.
20 25 35
20 25 35
10 12 15
20 25 35
8 10 15
8 10 15
8 10 12
20 25 35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Mode E1-Controlled
Data Retention Mode E2-Controlled
4.5 V
VCC
4.5 V
VCC
2.2 V
tDR
0V
VCC(DR) ≥ 2 V
Data Retention
2.2 V
trec
E1
VCC(DR) ≥ 2 V
E2
tDR
Data Retention
trec
0.8 V
0.8 V
0V
VE2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V
VCC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V
VE1(DR) ≥ VCC(DR) - 0.2 V or VE1(DR) ≤ 0.2 V
VE2(DR) ≤ 0.2 V
Chip Deselect to Data Retention Time
Operating Recovery Time at VCC(DR)
tDR:
min 0 ns
trec:
min tcR
4
December 12, 1997
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