U62H64DG25L Просмотр технического описания (PDF) - Zentrum Mikroelektronik Dresden AG
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U62H64DG25L Datasheet PDF : 8 Pages
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U62H64
Features
F Fast 8192 x 8 bit static CMOS
RAM
F 20 ns, 25 ns, 35 ns Access Times
F Bidirectional data inputs and
data outputs
F Three-state outputs
F Data retention current
at 3 V: < 10 µA (standard)
F Standby current standard < 30 µA
F Standby current low power (L)
< 5 µA
F TTL/CMOS-compatible
F Automatic reduction of power
dissipation in long
Read or Write cycles
F Power supply voltage 5 V
F Operating temperature ranges:
0 to 70 °C
-25 to 85 °C
F -40 to 85 °C
Quality assessment according to
CECC 90000, CECC 90100 and
F CECC 90111
ESD protection > 2000 V
(MIL STD 883C M3015.7)
F Latch-up immunity > 200 mA
F Packages: PDIP28 (300 mil)
SOJ28 (300 mil)
Description
The U62H64 is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read - Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
(E1 = L and E2 = H), each address
change leads to a new Read or
Write cycle. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
Fast 8K x 8 SRAM
the outputs DQ0 - DQ7. After the
address change, the data outputs
go High-Z until the new read infor-
mation is available. The data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the ope-
rating current (at IO = 0 mA) drops to
the value of the operating current in
the Standby mode. The Read cycle
is finished by the falling edge of E2
or W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V.
With the exception of E1 and E2, all
inputs consist of NOR gates, so that
no pull-up/pull-down resistors are
required. This gate circuit allows to
achieve low power standby require-
ments by activation with TTL-levels
too.
Pin Configuration
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7 PDIP 22
8 SOJ 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
December 12, 1997
1
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