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IDT7188S45DB

CMOS Static RAM 64K (16K x 4-Bit)

Integrated Device Technology 

IDT7188S/L

CMOS Static RAM 64K (16K x 4-Bit)

Military Temperature Range

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,5)

tWC

ADDRESS

CS

tAS

WE

DATAIN

tAW

tCW

t WR

tDW

tDH

DATA VALID

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. During this period, I/O pins are in the output state so that the input signals should not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.

6. Transition is measured ±200mV from steady state.

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Ordering Information

IDT 7188

Device

Type

X

XX

Power Speed

X

Package

X

Process/

Temperature

Range

B

Military (-55°C to +125°C)

,

Compliant to MIL-STD-883, Class B

D

300 mil Ceramic DIP (D22-1)

25

35

45

55

Speed in nanoseconds

70

85

S

Standard Power

L

Low Power

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6.472

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