IDT7188L45DB Просмотр технического описания (PDF) - Integrated Device Technology
Номер в каталоге
Компоненты Описание
Список матч
IDT7188L45DB Datasheet PDF : 8 Pages
| |||
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit)
Military Temperature Range
AC Electrical Characteristics (VCC = 5.0V ± 10%)
Symbol
Parameter
7188S25
7188L25
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC Write Cycle Time
20
____
30
____
40
____
50
____
60
____
75
____
ns
tCW Chip Select to End-of-Write
20
____
25
____
35
____
50
____
60
____
75
____
ns
tAW Address Valid to End-of-Write
20
____
25
____
35
____
50
____
60
____
75
____
ns
tAS Address Set-up Time
0
____
0
____
0
____
0
____
0
____
0
____
ns
tWP Write Pulse Width
20
____
25
____
35
____
50
____
60
____
75
____
ns
tWR Write Recovery Time
0
____
0
____
0
____
0
____
0
____
0
____
ns
tDW Data Valid to End-of-Write
13
____
15
____
20
____
25
____
30
____
35
____
ns
tDH Data Hold Time
0
____
0
____
0
____
0
____
0
____
0
____
ns
tWZ(1) Write Enable to Output in High-Z ____
7
____
10
____
15
____
25
____
30
____
40
ns
tOW(1) Output Active from End-of-Write
5
____
5
____
5
____
5
____
5
____
5
____
ns
NOTE:
1. This parameter is guaranteed by device characterization.
2989 tbl 12
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,3)
ADDRESS
tWC
tAW
CS1, CS2
tAS
tWP
tWR
WE
DATAOUT
tWZ (6)
(4)
tOW (6)
tDW
tDH
(4)
,
DATAIN
DATA VALID
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals should not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±200mV from steady state.
2989 drw 08
6
Share Link: 