MCM69L736AZP9.5 Просмотр технического описания (PDF) - Motorola => Freescale
Номер в каталоге
Компоненты Описание
производитель
MCM69L736AZP9.5 Datasheet PDF : 20 Pages
| |||
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0_C ≤ TA ≤ 70_C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.25 to 1.25 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 0.75 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 V
Clock Input Timing Reference Level . . . . . . Differential Cross–Point
RQ for 50 Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ω
READ/WRITE CYCLE TIMING (See Note 3)
MCM69L736A–7.5 MCM69L736A–8.5 MCM69L736A–9.5 MCM69L736A–10.5
MCM69L818A–7.5 MCM69L818A–8.5 MCM69L818A–9.5 MCM69L818A–10.5
Parameter
Symbol Min
Max
Min
Max
Min
Max
Min
Max Unit Notes
Cycle Time
tKHKH
7
—
8
—
9
—
Clock High Pulse Width tKHKL
2.8
—
3.2
—
3.6
—
Clock Low Pulse Width tKLKH
2.8
—
3.2
—
3.6
—
Clock High to Output
tKHQV
—
7.5
—
8.5
—
9.5
Valid
10
—
ns
4
—
ns
4
—
ns
—
10.5
ns
2
Clock Low to Output
tKLQV
—
3.5
—
4
—
4
—
4
ns
2
Valid
Clock Low to Output
tKLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
2
Hold
Clock Low to Output
tKLQX1
1
—
1
—
1
—
1
—
ns
3
Low–Z
Clock High to Output
tKHQZ
—
3.5
—
4
—
4
—
4
ns
3
High–Z
Output Enable Low to
tGLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
3
Output Low–Z
Output Enable Low to
tGLQV
—
3.5
—
4
—
4
—
4
ns
2
Output Valid
Output Enable to Output tGHQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
2
Hold
Output Enable High to
tGHQZ
—
3.5
—
4
—
4
—
4
ns
3
Output High–Z
Setup Times: Address tAVKH
0.5
—
0.5
—
0.5
—
0.5
—
ns
Data In tDVKH
Chip Select tSVKH
Write Enable tWVKH
Hold Times: Address tKHAX
1
—
1
—
1
—
1
—
ns
Data In tKHDX
Chip Select tKHSX
Write Enable tKHWX
NOTES:
1. Measured at ± 200 mV from steady state.
2. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications
(e.g., tKHKL) or at frequencies that exceed the applied K clock frequency.
3. Tested per AC Test Load diagram. See Figure 1.
0.75 V
Vref
DEVICE
UNDER
TEST
ZQ
50 Ω
250 Ω
VDDQ/2
50 Ω
TIMING LIMITS
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, ad-
dress setup time is shown as a minimum since the system
must supply at least that much time. On the other hand, re-
sponses from the memory are specified from the device
point of view. Thus, the access time is shown as a maximum
since the device never provides data later than that time.
Figure 1. AC Test Load
MCM69L736A•MCM69L818A
8
MOTOROLA FAST SRAM
Share Link: 