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IR3Y48M

CCD Signal Process & Digital Interface IC

Sharp Electronics 

Clamp Circuit

DC CLAMP

DC level of the analog input is fixed by internal DC

clamp circuit. DC level of C-coupled CCD signal at

CDS input is set to CLPCAP by DC clamping.

IR3Y48M

Normally clamp switch is turned on at black level

calibration period. Place 0.1 µF external

capacitance between CLPCAP and AVSS.

SHR SHD CCDCLP

Clamp Timing

REFIN

CCDIN

Timing Control

(Register Conditions)

CCD

(CCDCLP) Clamp

Source

ADCK

CLPCAP

CCDCLP

DC Clamp Function

CLPCAP

REFIN, CCDIN

Clamp Level

CLPCAP Level

CLAMP OF ADIN SIGNAL

Clamp operation for ADIN path is also available.

Note that clamp voltage [CLPCAP] is different

between CCD input and ADIN.

ADCLP signal is used for both clamp and black

level control at ADIN input mode. It is also possible

to turn off clamp operation by register setting.

CLAMP CONTROL

Following items are selectable through register

setting.

a) Clamp current

Normal or fast clamp is selectable for charge

current. (Select normal clamp in general)

b) Clamp target

Input signal (REFIN and CCDIN) to be

clamped is selectable. It is also possible to turn

off the clamp function.

ADCLP

Timing Control

ADIN

To AGC

or

To ADC

(ADCLP)

CLPCAP

ADIN DC Clamp Function

8

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