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W78E51B

8-BIT MTP MICROCONTROLLER

Winbond 

Preliminary W78E51B

Watchdog Timer Control Register

Bit:

7

6

5

4

ENW CLRW WIDL -

3

2

1

0

-

PS2 PS1 PS0

Mnemonic: WDTC

Address: 8FH

ENW : Enable watch-dog if set.

CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically

WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled

under IDLE mode. Default is cleared.

PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:

PS2 PS1 PS0

00 0

01 0

00 1

01 1

10 0

10 1

11 0

11 1

PRESCALER SELECT

2

4

8

16

32

64

128

256

The time-out period is obtained using the following equation :

1 × 214 × PRESCALER ×1000 ×12 mS

OSC

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6

(CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next

instruction cycle. The Watchdog timer is cleared on reset.

WIDL

IDLE

OSC

1/12

ENW

EXTERNAL

RESET

PRESCALER

14-BIT TIMER

CLEAR

INTERNAL

RESET

Watchdog Timer Block Diagram

CLRW

Publication Release Date: December 1998

-7-

Revision A1

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