IDT54FCT88915TT133PY Просмотр технического описания (PDF) - Integrated Device Technology
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IDT54FCT88915TT133PY Datasheet PDF : 11 Pages
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORM
50Ω to VCC/2, CL = 20pF
VCC
VCC
VIN
Pulse
Generator
D.U.T.
RT
VOUT
100Ω
100Ω
ENABLE AND DISABLE TEST CIRCUIT
VCC
7.0V
20pF
VIN
Pulse
Generator
V OUT
D.U.T.
500Ω
50pF
500Ω
RT
CL
3072 drw 11
PROPAGATION DELAY, OUTPUT SKEW
3072 lnk 12
SYNC INPUT
(SYNC (1) or
SYNC (0))
FEEDBACK
INPUT
Q/2 OUTPUT
tSKEWALL
Q0-Q4
OUTPUTS
Q5 OUTPUT
t CYCLE SYNC INPUT
tPD
t SKEWf
t SKEWr
t SKEWf
t CYCLE "Q" OUTPUTS
1.5V
1.5V
1.5V
t SKEWr
1.5V
1.5V
2Q OUTPUT
1.5V
3072 drw 13
NOTES:
(These waveforms represent the hookup of Figure 2a)
1. The FCT88915TT aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the 1.5V crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation
around a center point.
3. If a Q output is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q
output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
t PZL
SWITCH
CLOSED
t PZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
1.5V
1.5V
0V
1.5V
t PLZ
0V
3.5V
t PHZ
0.3V VOL
0.3V VOH
0V
NOTES:
3072 drw 14
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns
SWITCH POSITION
Test
Switch
Disable Low
Closed
Enable Low
Disable High
Open
Enable High
DEFINITIONS:
3072 tbl 10
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
9.7
10
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