SPT7861 Просмотр технического описания (PDF) - Signal Processing Technologies
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SPT7861 Datasheet PDF : 11 Pages
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Figure 1A – Timing Diagram 1
1
ANALOG IN
CLOCK IN
3
5
9
7
SAMPLING
CLOCK
(Internal)
DATA OUTPUT
DATA VALID
INVALID
11
13
17
15
VALID
1 2 3 45
Figure 1B – Timing Diagram 2
CLOCK IN
tCLK
tC
tCH
tCL
DATA Data 0
OUTPUT
Data 1
DATA VALID
tOD
tS
tS
tCH
Data 2
tCL
Data 3
Table I – Timing Parameters
DESCRIPTION
PARAMETERS MIN TYP MAX UNITS
Conversion Time
tC
tCLK
ns
Clock Period
tCLK
25
ns
Clock High Duty Cycle
tCH
40
50
60
%
Clock Low Duty Cycle
tCL
40
50
60
%
Clock to Output Delay (15 pF Load)
tOD
17
ns
Clock to DAV
tS
10
ns
SPT
5
SPT7861
6/25/01
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