SN74LS160A Просмотр технического описания (PDF) - ON Semiconductor
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SN74LS160A Datasheet PDF : 7 Pages
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STATE DIAGRAM
LS160A • LS162A
0
1
2
3
4
15
5
14
6
SN74LS160A
LS161A • LS163A
0
1
2
3
4
15
5
14
6
LOGIC EQUATIONS
Count Enable = CEP w CET w PE
TC for LS160A & LS162A = CET w Q0 w Q1 w Q2 w Q3
TC for LS161A & LS163A = CET w Q0 w Q1 w Q2 w Q3
Preset = PE w CP + (rising clock edge)
Reset = MR (LS160A & LS161A)
Reset = SR w CP + (rising clock edge)
Reset = (LS162A & LS163A)
13
7
13
7
12
11
10
9
8
12
11
10
9
8
NOTE:
The LS160A and LS162A can be preset to any state, but will not count
beyond 9. If preset to state 10, 11, 12, 13, 14, or 15, it will return to its
normal sequence within two clock pulses.
FUNCTIONAL DESCRIPTION
The LS160A / 161A / 162A / 163A are 4-bit synchronous
counters with a synchronous Parallel Enable (Load) feature.
The counters consist of four edge-triggered D flip-flops with
the appropriate data routing networks feeding the D inputs.
All changes of the Q outputs (except due to the
asynchronous Master Reset in the LS160A and LS161A)
occur as a result of, and synchronous with, the LOW to HIGH
transition of the Clock input (CP). As long as the set-up time
requirements are met, there are no special timing or activity
constraints on any of the mode control or data inputs.
Three control inputs — Parallel Enable (PE), Count Enable
Parallel (CEP) and Count Enable Trickle (CET) — select the
mode of operation as shown in the tables below. The Count
Mode is enabled when the CEP, CET, and PE inputs are
HIGH. When the PE is LOW, the counters will synchronously
load the data from the parallel inputs into the flip-flops on the
LOW to HIGH transition of the clock. Either the CEP or CET
can be used to inhibit the count sequence. With the PE held
HIGH, a LOW on either the CEP or CET inputs at least one
set-up time prior to the LOW to HIGH clock transition will
cause the existing output states to be retained. The AND
feature of the two Count Enable inputs (CET • CEP) allows
synchronous cascading without external gating and without
delay accumulation over any practical number of bits or
digits.
The Terminal Count (TC) output is HIGH when the Count
Enable Trickle (CET) input is HIGH while the counter is in its
maximum count state (HLLH for the BCD counters, HHHH
for the Binary counters). Note that TC is fully decoded and
will, therefore, be HIGH only for one count state.
The LS160A and LS162A count modulo 10 following a
binary coded decimal (BCD) sequence. They generate a TC
output when the CET input is HIGH while the counter is in
state 9 (HLLH). From this state they increment to state 0
(LLLL). If loaded with a code in excess of 9 they return to their
legitimate sequence within two counts, as explained in the
state diagram. States 10 through 15 do not generate a TC
output.
The LS161A and LS163A count modulo 16 following a
binary sequence. They generate a TC when the CET input is
HIGH while the counter is in state 15 (HHHH). From this state
they increment to state 0 (LLLL).
The Master Reset (MR) of the LS160A and LS161A is
asynchronous. When the MR is LOW, it overrides all other
input conditions and sets the outputs LOW. The MR pin
should never be left open. If not used, the MR pin should be
tied through a resistor to VCC, or to a gate output which is
permanently set to a HIGH logic level.
The active LOW Synchronous Reset (SR) input of the
LS162A and LS163A acts as an edge-triggered control input,
overriding CET, CEP and PE, and resetting the four counter
flip-flops on the LOW to HIGH transition of the clock. This
simplifies the design from race-free logic controlled reset
circuits, e.g., to reset the counter synchronously after
reaching a predetermined value.
MODE SELECT TABLE
*SR PE CET CEP Action on the Rising Clock Edge ( )
L
X
X
X
H
L
X
X
HH H
H
HH
L
X
HH X
L
RESET (Clear)
LOAD (Pn → Qn)
COUNT (Increment)
NO CHANGE (Hold)
NO CHANGE (Hold)
http://onsemi.com
2
*For the LS162A and
*LS163A only.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
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