DEVICE
UNDER
TEST
VDDQ/2
50 Ω
50 Ω
TIMING LIMITS
The table of timing values shows either a mini-
mum or a maximum limit for each parameter. Input
requirements are specified from the external system
point of view. Thus, address setup time is shown as
a minimum since the system must supply at least
that much time. On the other hand, responses from
the memory are specified from the device point of
view. Thus, the access time is shown as a maximum
since the device never provides data later than that
time.
Figure 1. AC Test Load
VOH
VSS
50%
100%
20% tKHKH
Figure 2. Undershoot Voltage
VDDQ
VTR
VDIF
CROSSING POINT
VCP
VCM*
VSS
*VCM, the Common Mode Input Voltage, equals VTR – ((VTR – VCP)/2).
Figure 3. Differential Inputs/Common Mode Input Voltage
MCM69L738A•MCM69L820A
8
MOTOROLA FAST SRAM