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74LVTH16646(2000) Просмотр технического описания (PDF) - Fairchild Semiconductor

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Компоненты Описание
Список матч
74LVTH16646
(Rev.:2000)
Fairchild
Fairchild Semiconductor Fairchild
74LVTH16646 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
Connection Diagram
Pin Descriptions
Pin Names
Description
A0–A15
Data Register A Inputs/3-STATE Outputs
B0–B15
Data Register B Inputs/3-STATE Outputs
CPABn, CPBAn Clock Pulse Inputs
SABn, SBAn
Select Inputs
OE1, OE2
Output Enable Inputs
DIRn
Direction Control Inputs
Truth Table(Note 1)
OE1
Inputs
DIR1 CPAB1 CPBA1 SAB1 SBA1
Data I/O
A0–7 B0–7
Output Operation Mode
H
H
H
X
X
X
H or L
  X
H or L
X
X
X
X
X
Isolation
X Input Input Clock An Data into A Register
X
Clock Bn Data Into B Register
L
L
H
H
X
X
X
L
L
L
L
H
H
H or L
X
X
H
H
L
L
L
L
X
X
X
X
X
L
L
L
L
X
X
H or L
X
X
H = HIGH Voltage Level
X = Immaterial
L = LOW Voltage Level
= LOW-to-HIGH Transition.
X
An to Bn—Real Time (Transparent Mode)
X Input Output Clock An Data to A Register
X
A Register to Bn (Stored Mode)
X
Clock An Data into A Register and Output to Bn
L
Bn to An—Real Time (Transparent Mode)
L Output Input Clock Bn Data into B Register
H
B Register to An (Stored Mode)
H
Clock Bn into B Register and Output to An
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control
pins.
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