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74ALVT16500

2.5V/3.3V 18-bit universal bus transceiver (3-State)

Philips Electronics 

Philips Semiconductors

2.5V/3.3V 18-bit universal bus transceiver (3-State)

Product specification

74ALVT16500

FEATURES

• 18-bit bidirectional bus interface

• 5V I/O Compatible

• 3-State buffers

• Output capability: +64mA/-32mA

• TTL input and output switching levels

• Input and output interface capability to systems at 5V supply

• Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

• Live insertion/extraction permitted

• Power-up reset

• Power-up 3-State

• No bus current loading when output is tied to 5V bus

• Negative edge-triggered clock inputs

• Latch-up protection exceeds 500mA per JEDEC JC40.2 Std 17

• ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

DESCRIPTION

The 74ALVT16500 is a high-performance BiCMOS product

designed for VCC operation at 2.5V and 3.3V with I/O compatibility

up to 5V.

This device is an 18-bit universal transceiver featuring non-inverting

3-State bus compatible outputs in both send and receive directions.

Data flow in each direction is controlled by output enable (OEAB and

OEBA), latch enable (LEAB and LEBA), and clock (CPAB and

CPBA) inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is High. When LEAB is Low, the A

data is latched if CPAB is held at a High or Low logic level. If LEAB

is Low, the A-bus data is stored in the latch/flip-flop on the

High-to-Low transition of CPAB. When OEAB is High, the outputs

are active. When OEAB is Low, the outputs are in the

high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA,

LEBA and CPBA. The output enables are complimentary (OEAB is

active High, and OEBA is active Low).

Active bus-hold circuitry is provided to hold unused or floating data

inputs at a valid logic level.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

tPLH

tPHL

CIN

CI/O

ICCZ

Propagation delay

An to Bn or Bn to An

Input capacitance DIR, OE

I/O pin capacitance

Total supply current

CONDITIONS

Tamb = 25°C; GND = 0V

CL = 50pF

VI = 0V or VCC

Outputs disabled; VI/O = 0V or VCC

Outputs disabled

TYPICAL

2.5V

3.3V

1.9

1.5

2.4

1.8

4

4

8

8

40

60

UNIT

ns

pF

pF

µA

ORDERING INFORMATION

PACKAGES

56-Pin Plastic SSOP Type III

56-Pin Plastic TSSOP Type II

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

–40°C to +85°C

74ALVT16500 DL

–40°C to +85°C

74ALVT16500 DGG

NORTH AMERICA

AV16500 DL

AV16500 DGG

DWG NUMBER

SOT371-1

SOT364-1

PIN DESCRIPTION

PIN NUMBER

1

27

2, 28

55,30

3, 5, 6, 8, 9, 10, 12, 13, 14, 15,

16, 17, 19, 20, 21, 23, 24, 26

54, 52, 51, 49, 48, 47, 45, 44, 43,

42, 41, 40, 38, 37, 36, 34, 33, 31

4, 11, 18, 25, 29, 32, 39, 46, 53, 56

7, 22, 35, 50

SYMBOL

OEAB

OEBA

LEAB/LEBA

CPAB/CPBA

A0-A17

B0-B17

GND

VCC

NAME AND FUNCTION

A-to-B Output enable input

B-to-A Output enable input (active low)

A-to-B/B-to-A Latch enable input

A-to-B/B-to-A Clock input (active falling edge)

Data inputs/outputs (A side)

Data inputs/outputs (B side)

Ground (0V)

Positive supply voltage

1998 Feb 13

2

853-1980 18959

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