74ALVC16836ADGG Просмотр технического описания (PDF) - NXP Semiconductors.
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74ALVC16836ADGG Datasheet PDF : 13 Pages
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Philips Semiconductors
20-bit registered driver with inverted register enable
(3-State)
Product specification
74ALVC16836A
AC CHARACTERISTICS FOR VCC = 2.3 V TO 2.7 V RANGE
GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF
SYMBOL
PARAMETER
WAVEFORM
Propagation delay
An to Yn
1, 7
tPHL/tPLH
Propagation delay
LE to Yn
2, 7
Propagation delay
CP to Yn
4, 7
tPZH/tPZL
3-State output enable time
OE to Yn
6, 7
tPHZ/tPLZ
3-State output disable time
OE to Yn
6, 7
CP pulse width HIGH or LOW
4, 7
tW
LE pulse width HIGH
2, 7
Set-up time An to CP
5, 7
tSU
Set-up time An to LE
3, 7
Hold time An to CP
5, 7
th
Hold time An to LE
3, 7
fmax
Maximum clock pulse frequency
4, 7
NOTE:
1. All typical values are at VCC = 3.3 V and Tamb = 25°C.
LIMITS
VCC = 2.3 to 2.7 V
MIN
TYP1
MAX
1.0
2.4
4.2
1.3
2.8
4.5
1.4
2.8
5.0
1.4
2.2
4.0
1.4
2.0
4.5
2.0
–
–
2.0
–
–
1.0
–
–
1.5
–
–
0.6
0.2
–
1.4
0.4
–
150
300
–
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3 ± 0.3 V
MIN TYP1, 2 MAX
Propagation delay
An to Yn
1, 7
1.0
2.3
3.6
tPHL/tPLH
Propagation delay
LE to Yn
2, 7
1.3
2.6
4.2
Propagation delay
CP to Yn
4, 7
1.3
2.5
4.2
tPZH/tPZL
3-State output enable time
OE to Yn
6, 7
1.1
2.3
4.4
tPHZ/tPLZ
3-State output disable time
OE to Yn
6, 7
1.3
2.8
4.3
CP pulse width HIGH or LOW
tW
LE pulse width HIGH
4, 7
2.0
–
–
2, 7
2.0
–
–
Set-up time An to CP
tSU
Set-up time An to LE
5, 7
1.0
–
–
3, 7
1.5
–
–
Hold time An to CP
th
Hold time An to LE
5, 7
0.9
0.3
–
3, 7
1.4
0.3
–
fmax
Maximum clock pulse frequency
NOTES:
1. All typical values are measured Tamb = 25°C.
2. Typical value is measured at VCC = 3.3 V
4, 7
150
300
–
LIMITS
VCC = 2.7 V
MIN TYP1 MAX
1.3
2.7
4.0
1.3
2.8
4.5
1.3
2.7
4.5
1.4
3.0
4.5
1.4
3.1
4.3
2.0
–
–
2.0
–
–
1.0
–
–
1.5
–
–
0.6
0.3
–
1.7
0.4
–
200
350
–
UNIT
ns
ns
ns
ns
ns
ns
MHz
UNIT
ns
ns
ns
ns
ns
ns
MHz
2000 Mar 14
7
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