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IDT7280
(Rev.:1996)

CMOS DUAL ASYNCHRONOUS FIFO DUAL 256 x 9, DUAL 512 x 9, DUAL 1024 x 9

Integrated Device Technology 

IDT7280/7281/7282 CMOS DUAL ASYNCHRONOUS FIFO

DUAL 256 x 9, DUAL 512 x 9 and DUAL 1K x 9

PRELIMINARY INFORMATION

COMMERCIAL TEMPERATURE RANGE

t XI

t XIR

XI

t XIS

WRITE TO

FIRST PHYSICAL

W

LOCATION

R

t XIS

READ FROM

FIRST PHYSICAL

LOCATION

Figure 11. Expansion In

3208 drw 13

OPERATING MODES:

Care must be taken to assure that the appropriate flag is

monitored by each system (i.e. FF is monitored on the device

where W is used; EF is monitored on the device where R is

used).

flags (EF, FF and HF) can be detected from any one FIFO.

Figure 13 demonstrates an 18-bit word width by using the two

FIFOs contained in the IDT7280/7281/7282s. Any word width

can be attained by adding FIFOs (Figure 13).

Single Device Mode

A single IDT7280/7281/7282 may be used when the appli-

cation requirements are for 256/512/1024 words or less. The

IDT7280/7281/7282 is in a Single Device Configuration when

the Expansion In (XI) control input is grounded (see Figure

12).

Bidirectional Operation

Applications which require data buffering between two

systems (each system capable of Read and Write operations)

can be achieved by pairing IDT7280/7281/7282s as shown in

Figure 16. Both Depth Expansion and Width Expansion may

be used in this mode.

Depth Expansion

The IDT7280/7281/7282 can easily be adapted to applica-

tions when the requirements are for greater than 256/512/

1024 words. Figure 14 demonstrates a four-FIFO Depth

Expansion using two IDT7280/7281/7282s. Any depth can be

attained by adding additional IDT7280/7281/7282s. The

IDT7280/7281/7282 operates in the Depth Expansion mode

when the following conditions are met:

1. The first FIFO must be designated by grounding the First

Load (FL) control input.

2. All other FIFOs must have FL in the high state.

3. The Expansion Out (XO) pin of each device must be tied to

the Expansion In (XI) pin of the next device. See Figure 14.

4. External logic is needed to generate a composite Full Flag

(FF) and Empty Flag (EF). This requires the ORing of all

EFs and ORing of all FFs (i.e. all must be set to generate the

correct composite FF or EF). See Figure 14.

5. The Retransmit (RT) function and Half-Full Flag (HF) are

not available in the Depth Expansion Mode.

Data Flow-Through

Two types of flow-through modes are permitted, a read

flow-through and write flow-through mode. For the read flow-

through mode (Figure 17), the FIFO permits a reading of a

single word after writing one word of data into an empty FIFO.

The data is enabled on the bus in (tWEF + tA) ns after the rising

edge of W, called the first write edge, and it remains on the

bus until the R line is raised from low-to-high, after which the

bus would go into a three-state mode after tRHZ ns. The EF line

would have a pulse showing temporary deassertion and then

would be asserted.

In the write flow-through mode (Figure 18), the FIFO

permits the writing of a single word of data immediately after

reading one word of data from a full FIFO. The R line causes

the FF to be deasserted but the W line being low causes it to

be asserted again in anticipation of a new data word. On the

rising edge of W, the new word is loaded in the FIFO. The W

line must be toggled when FF is not asserted to write new data

in the FIFO and to increment the write pointer.

USAGE MODES:

Width Expansion

Word width may be increased simply by connecting the

corresponding input control signals of multiple FIFOs. Status

Compound Expansion

The two expansion techniques described above can be

applied together in a straightforward manner to achieve large

FIFO arrays (see Figure 15).

5.07

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