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ICS650-01B

System Peripheral Clock Source

Integrated Circuit Systems 

ICS650-01B

System Peripheral Clock Source

Electrical Specifications

Parameter

Conditions

ABSOLUTE MAXIMUM RATINGS (note 1)

Minimum

Supply voltage, VDD

Referenced to GND

Inputs and Clock Outputs

Referenced to GND

-0.5

Ambient Operating Temperature

0

Soldering Temperature

Max of 10 seconds

Storage temperature

-65

DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)

Operating Voltage, VDD

3.0

Input High Voltage, VIH

Select inputs, OE

2

Input Low Voltage, VIL

Select inputs, OE

Output High Voltage, VOH

VDD=3.3V, IOH=-8mA 2.4

Output Low Voltage, VOL

VDD=3.3V, IOL=8mA

Output High Voltage, VOH, VDD = 3.3 or 5V IOH=-8mA

VDD-0.4

Operating Supply Current, IDD, at 5V

No Load, note 2

Operating Supply Current, IDD, at 3.3V

No Load, note 2

Short Circuit Current, VDD = 3.3

Each output

Input Capacitance

Except X1

AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)

Input Crystal or Clock Frequency

Output Clocks Accuracy (synthesis error)

All clocks

Output Clock Rise Time

0.8 to 2.0V

Output Clock Fall Time

2.0 to 0.8V

Output Clock Duty Cycle

At VDD/2

40

One Sigma Jitter

Except ACLK

One Sigma Jitter

ACLK

Absolute Clock Period Jitter

PCLK, UCLK, BCLK

- 500

Typical

50

25

±50

7

14.31818

50

75

170

Maximum Units

7

V

VDD+0.5 V

70

°C

260

°C

150

°C

5.5

V

V

0.8

V

V

0.4

V

V

mA

mA

mA

pF

MHz

1

ppm

1.5

ns

1.5

ns

60

%

ps

ps

500

ps

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. With all clocks at highest frequencies.

External Components

The ICS650 requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.01µF should be connected between VDD and GND (on pins 4 and 6, and pins 16 and 14),

as close to the chip as possible. A series termination resistor of 33 Ω may be used for each clock output. The

14.31818 MHz crystal must be connected as close to the chip as possible. The crystal should be a

fundamental mode, parallel resonant, 30 ppm or better (to meet the Ethernet specs). Crystal capacitors

should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by

the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-12) x 2. So for a

crystal with 16pF load capacitance, two 8pF caps should be used. If a clock input is used, drive it into X1

and leave X2 unconnected.

MDS 650-01B A

3

Revision 041499

Printed 11/15/00

Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • (408) 295-9818fax

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