V62C2162048L-55B Просмотр технического описания (PDF) - Mosel Vitelic Corporation

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V62C2162048L-55B

Ultra Low Power 128K x 16 CMOS SRAM

Mosel Vitelic Corporation  

V62C2162048L(L)

DC Operating Characteristics (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)

Parameter

Input Leakage Current

Output Leakage

Current

Sym Test Conditions

IILII

Vcc = Max,

Vin = Gnd to Vcc

-55

-70

-85

Min Max Min Max Min Max

-1-1-1

-100

Unit

Min Max

- 1 µA

IILOI

CE = VIH or Vcc= Max,

VOUT = Gnd to Vcc

- 1 - 1 - 1 - 1 µA

Operating Power

Supply Current

ICC CE = VIL , VIN = VIH or VIL ,

-

5

-

5

-

5

-

5 mA

IOUT = 0

Average Operating

Current

ICC1 IOUT = 0mA,

Min Cycle, 100% Duty

- 50 - 45 - 40 - 40 mA

ICC2 CE < 0.2V

IOUT = 0mA,

- 3 - 3 - 3 - 3 mA

Cycle Time=1µs, Duty=100%

Standby Power Supply ISB CE = VIH

Current (TTL Level)

- 0.5 - 0.5 - 0.5 - 0.5 mA

Standby Power Supply ISB1 CE > Vcc - 0.2V

Current (CMOS

VIN < 0.2V or

Level)

VIN > Vcc- 0.2V

- 10 - 10 - 10 - 10 µA

L-

2

-

2

-

2

-

2

µA

Output Low Voltage

VOL IOL = 2 mA

- 0.4 - 0.4 - 0.4 - 0.4 V

Output High Voltage VOH IOH = -2 mA

2.4 - 2.4 - 2.4 - 2.4 -

V

Capacitance (f = 1MHz, TA = 25oC)

Parameter*

Input Capacitance

I/O Capacitance

Symbol

Cin

CI/O

Test Condition

Vin = 0V

Vin = Vout = 0V

Max

7

8

Unit

pF

pF

* This parameter is guaranteed by device characterization and is not production tested.

AC Test Conditions

Input Pulse Level

0.6V to 2.2V

Input Rise and Fall Time 5ns

Input and Output Timing

Reference Level

1.4V

Output Load Condition

55ns/70ns/85ns

Load for 100ns

CL = 30pf + 1TTL Load

CL = 100pf + 1TTL Load

CL*

TTL

Figure A.

* Including Scope and Jig Capacitance

4

REV. 1.3 OCT 2001 V62C2162048L(L)

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