IDT74ALVC162244PV Просмотр технического описания (PDF) - Integrated Device Technology
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IDT74ALVC162244PV Datasheet PDF : 6 Pages
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IDT74ALVC162244
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
VCC
Pulse(1, 2)
V IN
Generator
VOUT
D.U.T.
500Ω
VLOAD
Open
GND
RT
500Ω
CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tP LH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
SAME PHASE
INPUT TRANSITION
tPLH
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
tPHL
Propagation Delay
V IH
VT
0V
VOH
VT
VOL
VIH
VT
0V
ALVC Link
CONTROL
IN PUT
ENABLE
tPZL
D IS A B LE
VIH
VT
tPLZ
0V
OUTPUT
SW ITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
VLOAD/2
VT
tPHZ
VT
0V
VLOAD/2
VOL + VLZ
VOL
VOH
VOH - VHZ
0V
ALVC Link
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DATA
INPUT
TIMING
IN P U T
ASYNCHRONOUS
C ON TR O L
tSU
tH
tREM
SYNCHRONOUS
C ON TR O L
tSU
tH
Set-up, Hold, and Release Times
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
ALVC Link
LO W -H IG H -LO W
PULSE
tW
HIGH-LOW -H IGH
PULSE
Pulse Width
VT
VT
ALV C Link
5
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