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AN4105

Design Considerations for Switched Mode Power Supplies Using A Fairchild Power Switch (FPS) in a Flyback Converter

Fairchild Semiconductor 

APPLICATION NOTE

AN4105

1 0V

2㎂

1㎃

FaFircahilrdcPhoiwlder SPwoitcwh(eFrPS)

Switch (SPS)

Fairchild Power SwitcSh(PFPSS)

1㎃

PWM

5V

Co mp a ra to r

Ds

－

5 0k

＋

#4

#5

KA5XX Series

Cs

A

Exte rna l

Syn c In p ut

Rs KKAA25SSXXX X

KAA35SQXXX X

B

S eries

Figure 6. Soft start circuit.

Note that when the voltage across CS exceeds 3V, The voltage

at the comparator’s inverting terminal no longer follows the

voltage across CS. Instead, it follows the output voltage

feedback signal. In shutdown or protection circuit operation,

capacitor CS is discharged, in order to enable it to charge from

0V at restart.

1.6 Synchronization

In an SMPS intended for use with monitors, synchronization

is handled differently than in a general purpose SMPS. For

monitor use, it is necessary to prevent noise from appearing on

the monitor display. To accomplish this, it is necessary to

synchronize the SMPS switching frequency with the

monitor’s horizontal sync frequency. The monitor’s horizontal

scan flyback signal is commonly used as the external sync

signal for the SMPS. By synchronizing the switching with the

horizontal scan’s flyback, the switching noise is positioned at

the far left of the monitor display where it cannot be seen.

Figure 7 shows how to implement the external circuit for

synchronization. The external sync signal, applied across

resistor Rs, cannot drop below 0.6V because of diode Dsync.

After the conclusion of the initial soft start, the voltage across

Cs remains at 5V until the external sync signal is applied, at

which point it looks like VRs of Figure 8. The sync comparator

compares VCs against a 6.3V level and produces the

comparator output waveform, Vcomp of Figure 8.

A Fairchild Power Switch (FPS) has an internal timing

capacitor, Ct. Figure 8 shows that when the voltage on Ct, VCt,

reaches an upper threshold, it begins to discharge; then, when

it reaches a lower threshold, it again starts to charge. This

operation is controlled by the internal oscillator. The oscillator

output signal, VCk in Figure 8, which goes low.

PW M

5V

co m p a ra to r

－

V CS

#5

＋

E xte rn a l

S ync

In p ut

Cs

V RS

Rs

Dsyn c

6 .3V

V C OMP

－

＋

OSC .

S ync

co m p a ra to r

Figure 7. Synchronization circuit.

when Ct recharges and high when it discharges, is applied to

the Fairchild Power Switch (FPS) S/R Latch Set terminal. In

the absence of an external sync signal, the voltage across Ct

oscillates at the basic frequency of 20kHz. In the presence of

a sync signal, however, the Set signal goes high because VCt

charges to the high threshold following the external sync

signal, and, ultimately, the Set signal, which determines the

switching frequency, synchronizes to the external sync

signal. It is necessary to limit the Set signal's high duration to

5% or less of the full cycle. As the Set signal drops low the

gate turns on. If the device were not synchronized to the

horizontal scan of the monitor, noise would appear on the

screen. When the Set signal goes high, the sync is synchro-

nized with the horizontal scan flyback. Because the high

duration is 5% (maximum) of the full cycle, the start of the

horizontal scan (as the Set signal goes low) turns on the

switch. The switch turn on noise, therefore, is hidden in the

horizontal blanking period at the far left of the monitor

display.

V RS

0V

2V

V CS

5V

0V

V COMP

0V

V CT

0V

V ThH

V ThL

V ck

0V

Figure 8. Synchronization circuit operation.

©2002 Fairchild Semiconductor Corporation

5

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