L9822E(2002) Просмотр технического описания (PDF) - STMicroelectronics

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L9822E
(Rev.:2002)

OCTAL SERIAL SOLENOID DRIVER

STMicroelectronics 

L9822E

FUNCTIONAL DESCRIPTION

The L9822ESP DMOS output is a low operating

power device featu-ring, eight 1Ω RDSON DMOS

drivers with transient protection circuits in output

stages. Each channel is independently controlled by

an output latch and a common RESET line which dis-

ables all eight outputs. The driver has low saturation

and short circuit protection and can drive inductive

and resistive loads such as solenoids, lamps and re-

lais. Data is transmitted to the device serially using

the Serial Peripheral Interface (SPI) protocol. The cir-

cuit receives 8 bit serial data by means of the serial

input (SI) which is stored in an internal register to con-

trol the output drivers. The serial output (SO) pro-

vides 8 bit of diagnostic data representing the voltage

level at the driver output. This allows the micropro-

cessor to diagnose the condition of the output drivers.

The output saturation voltage is monitored by a

comparator for an out of saturation condition and is

able to unlatch the particular driver through the fault

reset line. This circuit is also cascadable with an-

other octal driver in order to jam 8 bit multiple data.

The device is selected when the chip enable (CE)

line is low.

Additionally the (SO) is placed in a tri-state mode

when the device is deselected. The negative edge

of the (CE) transfers the voltage level of the drivers

to the shift register and the positive edge of the (CE)

latches the new data from the shift register to the

drivers. When CE is Low, data bit contained into the

shift register is transferred to SO output at every

SCLK positive transition while data bit present at SI

input is latched into the shift register on every SCLK

negative transition.

Internal Blocks Description

The internal architecture of the device is based on

the three internal major blocks : the octal shift reg-

ister for talking to the SPI bus, the octal latch for hold-

ing control bits written into the device and the octal

load driver array.

Shift Register

The shift register has both serial and parallel inputs

and serial and parallel outputs. The serial input ac-

cepts data from the SPI bus and the serial output

simultaneously sends data into the SPI bus. The

parallel outputs are latched into the parallel latch in-

side the L9822ESP at the end of a data transfer. The

parallel inputs jam diagnostic data into the shift reg-

ister at the beginning of a data transfer cycle.

Parallel Latch

The parallel latch holds the input data from the shift

register. This data then actuates the output stages.

Individual registers in the latch may be cleared by

fault conditions in order to protect the overloaded

output stages. The entire latch may also be cleared

by the RESET signal.

Output Stages

The output stages provide an active low drive signal

suitable for 0.75A continuous loads. Each output

has a current limit circuit which limits the maximum

output current to at least 1.05A to allow for high in-

rush currents. Additionally, the outputs have internal

zeners set to 36 volts to clamp inductive transients

at turn-off. Each output also has a voltage compara-

tor observing the output node. If the voltage exceeds

1.8V on an ON output pin, a fault condition is as-

sumed and the latch driving this particular stage is

reset, turning the output OFF to protect it. The timing

of this action is described below. These compara-

tors also provide diagnostic feedback data to the

shift register. Additionally, the comparators contain

an internal pulldown current which will cause the cell

to indicate a low output voltage if the output is pro-

grammed OFF and the output pin is open circuited.

TIMING DATA TRANSFER

Figure #2 shows the overall timing diagram from a

byte transfer to and from the L9822ESP using the

SPI bus.

CE High to Low Transition

The action begins when the Chip Enable (CE) pin is

pulled low. The tri-state Serial Output (SO) pin driver

will be enabled entire time that CE is low. At the fall-

ing edge of the CE pin, the diagnostic data from the

voltage comparators in the output stages will be

latched into the shift register. If a particular output is

high, a logic one will be jammed into that bit in the

shift register. If the output is low, a logic zero will be

loaded there. The most significant bit (07) should be

presented at the Serial Input (SI) pin. A zero at this

pin will program an output ON, while a one will pro-

gram the output OFF.

SCLK Transitions

The Serial Clock (SCLK) pin should then be pulled

high. At this point the diagnostic bit from the most

significant output (07) will appear at the SO pin. A

high here indicates that the 07 pin is higher than

1.8V. The SCLK pin should then be toggled low then

high. New SO data will appear following every rising

edge of SCLK and new SI data will be latched into

the L9822ESP shift register on the falling edges. An

unlimited amount of data may be shifted through the

device shift register (into the SI pin and out the SO

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