CDB5505 Просмотр технического описания (PDF) - Cirrus Logic

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CDB5505

Evaluation Board for CS5505/6/7/8 Series of ADCs

Cirrus Logic 

A0

CS

CONV

CAL

XIN

XOUT

M/SLP

BU/UP

AIN1+

AIN2+/NC

AIN-

AIN3+

1 CS5505/6 24

2/1

20/23

CS5507/8

3/2

19/22

4/3

18/21

5/4

17/20

6/5

16/19

7/6

15/18

8/7

14/17

9/8

13/16

10/9

12/15

11/10

11/14

12

13

A1

DRDY

SDATA

SCLK

VD+

DGND

VA-

VA+

VREFOUT

VREF-

VREF+

AIN4+

Figure 2. CS5505/6 and CS5507/8 Pin Layouts

for A0 and A1 (see Table 1). Once A0 and A1

are selected, the CONV switch (S2-3) must be

switched on (closed) and then open to cause the

CONV signal to transition low to high. This

latches the A0 and A1 channel selection into the

converter. With CONV high (S2-3 open) the

converter will convert continuously.

Figures 3 and 4 illustrate the evaluation board

layout while Figure 5 illustrates the component

placement (silkscreen) of the evaluation board.

CDB5505/6/7/8

CS5505/6/7/8

36

DS59DB32

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