MC74HC4020A Просмотр технического описания (PDF) - Motorola => Freescale
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MC74HC4020A Datasheet PDF : 8 Pages
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MC74HC4020A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V –55 to 25°C ≤85°C
≤125°C Unit
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
30
3.0
20
4.5
5
6.0
4
40
50
ns
25
30
8
12
6
9
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
70
3.0
40
4.5
15
6.0
13
80
90
ns
45
50
19
24
16
20
tw
Minimum Pulse Width, Reset
(Figure 2)
2.0
70
3.0
40
4.5
15
6.0
13
80
90
ns
45
50
19
24
16
20
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
1000
3.0
800
4.5
500
6.0
400
1000
800
500
400
1000
ns
800
500
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
Clock (Pin 10)
Negative–edge triggering clock input. A high–to–low tran-
sition on this input advances the state of the counter.
Reset (Pin 11)
Active–high reset. A high level applied to this input asynch-
ronously resets the counter to its zero state, thus forcing all Q
outputs low.
OUTPUTS
Q1, Q4—Q14 (Pins 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3)
Active–high outputs. Each Qn output divides the Clock
input frequency by 2N.
SWITCHING WAVEFORMS
tf
tr
90%
VCC
Clock
50%
10%
GND
tw
1/fMAX
tPLH
tPHL
90%
Q1 50%
10%
tTLH
tTHL
Clock
Reset
Any Q
Figure 1.
VCC
50%
GND
trec
tw
VCC
50%
GND
tPHL
50%
Figure 2.
MOTOROLA
3–4
High–Speed CMOS Logic Data
DL129 — Rev 6
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