CY7C057V-15AXC_11 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C057V-15AXC_11

3.3 V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static RAM

Cypress Semiconductor 

CY7C056V

CY7C057V

Pin Definitions

Left Port

A0L–A13/14L

SEML

CE0L, CE1L

INTL

BUSYL

I/O0L–I/O35L

OEL

R/WL

B0–B3

M/S

VSS

VDD

Right Port

A0R–A13/14R

SEMR

CE0R, CE1R

INTR

BUSYR

I/O0R–I/O35R

OER

R/WR

BM, SIZE

WA, BA

Description

Address (A0–A13 for 16K; A0–A14 for 32K devices)

Semaphore Enable

Chip Enable (CE is LOW when CE0  VIL and CE1 VIH)

Interrupt flag

Busy flag

Data bus input/output

Output Enable

Read/Write Enable

Byte select inputs. Asserting these signals enables read and write operations

to the corresponding bytes of the memory array.

See bus matching for details.

See bus matching for details.

Master or Slave select

Ground

Power

Document #: 38-06055 Rev. *E

Page 6 of 26

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