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CY7C056V-15AI_11 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C056V-15AI_11 Datasheet PDF : 26 Pages
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CY7C056V CY7C057V CY7C037V CY7C038V3.3 V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static RAM
CY7C056V
CY7C057V
3.3 V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static
RAM
Features
True dual-ported memory cells that allow simultaneous
access of the same memory location
16K x 36 organization (CY7C056V)
32K x 36 organization (CY7C057V)
0.25-micron Complimentary metal oxide semiconductor
(CMOS) for optimum speed/power
High-speed access: 12/15 ns
Low operating power
Active: ICC = 250 mA (typical)
Standby: ISB3 = 10 A (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 72 bits or more using Master/Slave
Chip Select when using more than one device
Logic Block Diagram
R/WL
B0–B3
CE0L
CE1L
OEL
Left
Port
CEL
Control
Logic
9
I/O0L–I/O8L
9
I/O9L–I/O17L
9
I/O18L–I/O26L
9
I/O27L–I/O35L
I/O
Control
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Byte select on left port
Bus matching on right port
Depth expansion via dual chip enables
Pin select for Master or Slave
Commercial and Industrial temperature ranges
Available in 144-Pin Thin quad plastic flatpack (TQFP) or
172-Ball ball grid array (BGA)
Pb-free packages available
Compact packages:
144-Pin TQFP (20 x 20 x 1.4 mm)
172-Ball BGA (1.0-mm pitch) (15 x 15 x.51 mm)
I/O
Control
Right
Port
Control
Logic
CER
9
9
Bus
9
Match
9
R/WR
CE0R
CE1R
OER
BA
WA
9/18/36
I/OR
BM
SIZE
A0L–A13/14[L1]
14/15
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
14/15
A0R–A13/14R[1]
14/15
14/15
SEML
BUSYL[2]
INTL
Notes
1. A0–A13 for 16K; A0–A14 for 32K devices.
2. BUSY is an output in Master mode and an input in Slave mode.
Interrupt
Semaphore
Arbitration
M/S
SEMR
BUSYR[2]
INTR
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06055 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 30, 2011
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