CY7C057V-15AXC_11 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C057V-15AXC_11 Datasheet PDF : 26 Pages
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CY7C056V
CY7C057V
Switching Characteristics Over the Operating Range[13] (continued)
Parameter
Description
Busy Timing[21]
tBHC
BUSY HIGH from CE HIGH
tPS
Port set-up for priority
tWB
R/W LOW after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[22]
BUSY HIGH to data valid
Interrupt Timing[21]–
tINS
INT set time
tINR
INT reset time
Semaphore Timing
tSOP
tSWRD
tSPS
tSAA
SEM flag update pulse (OE or SEM)
SEM flag write to read time
SEM flag contention window
SEM address access time
Data Retention Mode
CY7C056V
CY7C057V
-12
-15
Unit
Min
Max
Min
Max
–
12
–
15
ns
5
–
5
–
ns
0
–
0
–
ns
11
–
13
–
ns
–
12
–
15
ns
–
12
–
15
ns
–
12
–
15
ns
10
–
10
–
ns
5
–
5
–
ns
5
–
5
–
ns
–
12
–
15
ns
The CY7C056V and CY7C057V are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip Enable (CE)[23] must be held HIGH during data retention,
within VDD to VDD – 0.2 V.
2. CE must be kept between VDD – 0.2 V and 70% of VDD during
the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VDD reaches the
minimum operating voltage (3.15 volts).
Timing
Data Retention Mode
VCC
3.15 V VCC 2.0 V 3.15 V
tRC
CE
VCC to VCC – 0.2 V
VIH
Parameter
ICCDR1
Test Conditions[24]
@ VDDDR = 2 V
Max
50
Unit
A
Notes
21. Test conditions used are Load 1.
22. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
23. CE is LOW when CE0 VIL and CE1 VIH.
24. CE = VDD, Vin = VSS to VDD, TA = 25 C. This parameter is guaranteed but not tested.
Document #: 38-06055 Rev. *E
Page 11 of 26
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