CY7C056V-15AI_11 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C056V-15AI_11 Datasheet PDF : 26 Pages
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CY7C056V
CY7C057V
Switching Characteristics Over the Operating Range[13]
Parameter
Description
CY7C056V
CY7C057V
-12
-15
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
tOHA
tACE[14, 15]
Output hold from address change
CE LOW to data valid
tDOE
OE LOW to data valid
tLZOE[14, 16, 17, 18] OE Low to low Z
tHZOE[14, 16, 17, 18] OE HIGH to High Z
tLZCE[14, 13, 17, 18] CE LOW to Low Z
tHZCE[14, 16, 17, 18] CE HIGH to High Z
tLZBE
Byte Enable to Low Z
tHZBE
tPU[14, 18]
tPD[14, 18]
tABE[15]
Byte Enable to High Z
CE LOW to power-up
CE HIGH to power-down
Byte Enable access time
Write Cycle
12
–
15
–
ns
–
12
–
15
ns
3
–
3
–
ns
–
12
–
15
ns
–
8
–
10
ns
0
–
0
–
ns
–
10
–
10
ns
3
–
3
–
ns
–
10
–
10
ns
3
–
3
–
ns
–
10
–
10
ns
0
–
0
–
ns
–
12
–
15
ns
–
12
–
15
ns
tWC
tSCE[14, 15]
Write cycle time
CE LOW to write end
tAW
Address valid to write end
tHA
tSA[15]
Address hold from write end
Address set-up to write start
tPWE
Write pulse width
tSD
Data set-up to write end
tHD
Data hold from write end
tHZWE[17, 18]
R/W LOW to High Z
tLZWE[17, 18]
R/W HIGH to Low Z
tWDD[19]
Write pulse to data delay
tDDD[19]
Write data valid to read data valid
Busy Timing[20]
12
–
15
–
ns
10
–
12
–
ns
10
–
12
–
ns
0
–
0
–
ns
0
–
0
–
ns
10
–
12
–
ns
10
–
10
–
ns
0
–
0
–
ns
–
10
–
–
ns
3
–
3
–
ns
–
25
–
–
ns
–
20
–
25
ns
tBLA
BUSY LOW from address match
–
12
–
15
ns
tBHA
BUSY HIGH from address mismatch
–
12
–
15
ns
tBLC
BUSY LOW from CE LOW
–
12
–
15
ns
Notes
13.
Test
and
conditions
10-pF load
assume signal
capacitance.
transition
time
of
3
ns
or
less,
timing
reference
levels
of
1.5
V,
input
pulse
levels
of
0
to
3.0
V,
and
output
loading
of
the
specified
IOI/IOH
14. CE is LOW when CE0 VIL and CE1 VIH
15. To access RAM, CE = L and SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
17. Test conditions used are Load 2.
18. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer
to Read Timing with Busy waveform.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
20. Test conditions used are Load 1.
Document #: 38-06055 Rev. *E
Page 10 of 26
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