74LVT16952 Просмотр технического описания (PDF) - Fairchild Semiconductor
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74LVT16952 Datasheet PDF : 8 Pages
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Connection Diagram
Pin Descriptions
Pin Names
A0–A16
B0–B16
CPABn, CPBAn
CEAn, CEBn
OEABn, OEBAn
Truth Table
(Note 1)
Description
Data Register A Inputs
B-Register 3-STATE Outputs
Data Register B Inputs
A-Register 3-STATE Outputs
Clock Pulse Inputs
Clock Enable
Output Enable Inputs
Inputs
Internal Register Output
An CPABn CEAn OEABn
Value
Bn
XX
H
L
XX
H
H
L
L
L
L
H
L
L
H
L
H
L
H
NC
B0
NC
Z
L
L
L
Z
H
H
H
Z
XL
X
L
XH
X
L
XL
X
H
NC
B0
NC
B0
NC
Z
XH
X
H
NC
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = Output High Impedance
= LOW-to-HIGH Transition.
NC = No Change (state established by last valid CP)
B0 = State established by last valid CP
Note 1: A to B data flow shown; B to A flow control is the same, but used
OEBAn, CPBAn and CEBn.
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