IS61LV2568 Просмотр технического описания (PDF) - Integrated Silicon Solution

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IS61LV2568

256K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61LV2568

AC WAVEFORMS

WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)

t WC

ADDRESS

OE

VALID ADDRESS

t HA

ISSI ®

CE LOW

WE

t AW

t PWE1

DOUT

t SA

DATA UNDEFINED

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DIN

DATAIN VALID

CE_WR2.eps

Note:

1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any

can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that

terminates the Write.

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

ADDRESS

t WC

VALID ADDRESS

t HA

OE LOW

CE LOW

WE

DOUT

t SA

DATA UNDEFINED

t AW

t PWE2

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DIN

DATAIN VALID

CE_WR3.eps

Note:

1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any

can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that

terminates the Write.

Integrated Silicon Solution, Inc. — 1-800-379-4774

7

Rev. A

12/19/00

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