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TEA1753T

HV start-up DCM/QR flyback controller with integrated DCM/QR PFC controller

NXP Semiconductors. 

NXP Semiconductors

TEA1753T

HV start-up flyback controller with integrated PFC controller

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Fig 5. Soft-start-up of PFC

7.2.6 Low-power mode

When the output power of the flyback converter (see Section 7.3) is low, the flyback

converter switches over to frequency reduction mode. When the maximum switching

frequency of the flyback drops below 48 kHz, the power factor correction circuit is

switched off to maintain high efficiency. Connect a capacitor to the PFCTIMER pin to delay

switching off (see Section 7.2.7).

During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of

3.5 V or 2.5 V and a maximum voltage of 3.9 V. The lower clamp voltage depends on the

voltage on VINSENSE pin. This voltage limits the maximum power that is delivered when

the PFC is switched on again. The upper clamp voltage ensures that the PFC returns from

low-power mode to its normal regulation point in a limited time.

When the flyback converter frequency exceeds 86 kHz, the power factor correction circuit

restores normal operation.

7.2.7

PFC off delay (PFCTIMER pin)

When the flyback converter maximum frequency drops below 48 kHz, the PFC is

switched off. The IC then outputs a 5 A current to the PFCTIMER pin. When the voltage

on the PFCTIMER pin reaches 3.6 V, the PFC is switched off by performing a soft-stop.

When the flyback converter frequency exceeds 86 kHz, a switch discharges the

PFCTIMER pin capacitor. When the voltage on the PCTIMER pin drops below 1.27 V, the

PFC is switched on (see Figure 6).

TEA1753T

Product data sheet

low power

5 µA

3.6 V

1.27 V

R

Q

low power delay

S

(PFC on)

14 PFCTIMER

Fig 6. PFC start/stop via PPFCTIMER pin

All information provided in this document is subject to legal disclaimers.

Rev. 3. — 24 August 2012

014aaa740

© NXP B.V. 2012. All rights reserved.

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