GS9091B Просмотр технического описания (PDF) - Semtech Corporation

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GS9091B

GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI

Semtech Corporation 

Table 1-1: Ball List and Description (Continued)

Ball

Name

K7, K8, J8, J9 STAT[0:3]

K9

RD_CLK

Timing

Type Description

Synchronous

with PCLK or

RD_CLK

Output

MULTI FUNCTION I/O PORT

Signal levels are LVCMOS / LVTTL compatible.

Programmable multi-function outputs. By programming the bits is

the IO_CONFIG register, each pin can output one of the following

signals:

•H

•V

•F

• FIFO_LD

• ANC

• EDH_DETECT

• FIFO_FULL

• FIFO_EMPTY

These pins are set to certain default values depending on the

configuration of the device and the internal FIFO mode selected.

See Section 3.12 for details.

FIFO READ CLOCK

Signal levels are LVCMOS / LVTTL compatible.

–

Input

The application layer clocks the parallel data out of the FIFO on the

rising edge of RD_CLK.

GS9091B GenLINX® II 270Mb/s Deserializer for SDI

and DVB-ASI

Final Data Sheet

38910 - 3

February 2013

11 of 73

Proprietary & Confidential

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