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CS8130_94 Просмотр технического описания (PDF) - Cirrus Logic

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CS8130_94 Datasheet PDF : 28 Pages
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CS8130
Register 12, Output Pin Control Register
Register
Reset (R)
D3 D2 D1 D0
RXDT RXDH FORT FORH
0101
BIT
RXDT
RXDH
FORT
FORH
NAME
RXD output pin
three-state enable
RXD output pin
high/low enable
FORM/BSY output
pin three-state
enable
FORM/BSY output
pin high/low enable
VALUE
0
1
0
1
0
1
0
1
FUNCTION
R In power down, RXD will go high or low.
In power down, RXD will float.
In power down, RXD will go low, if RXDT = 0
R In power down, RXD will go high, if RXDT = 0
R In power down, FORM/BSY will go high or low.
In power down, FORM/BSY will float.
In power down, FORM/BSY will go low, if FORT = 0
R In power down, FORM/BSY will go high, if FORT = 0
Register 13, Control Register #3
Register
D3 D2 D1 D0
0
0
0 SHDW
Reset (R) 0 0 0 0
BIT
SHDW
NAME
Shadow register set
enable
VALUE
0
1
FUNCTION
R Enable access to registers 0 though 15
Enable access to shadow registers (16 through 31)
Register 15, Status Register
Register
Reset (R)
D3 D2 D1 D0
0 OSCR ERR DMOD
0
00
BIT
NAME
VALUE
FUNCTION
OSCR
Oscillator running
0
Oscillator not running, using external clock input,
flag
oscillator circuit is powered down.
1
Oscillator running, EXTCLK is an output, if enabled.
ERR
Framing error flag
0
R No error
1
A framing error has occurred since the last read of
this bit. Resets after read
DMOD
Detected
0
R IrDA pulse style data format detected
Modulation Type
1
Amplitude modulated carrier style data format
detected
To read this register, write 0000 to address 15. Independent of the setting of the ECHO bit, the CS8130
will transmit the above contents, with an address field of 1111.
18
DS134PP2

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