NLV14046BDWG Просмотр технического описания (PDF) - ON Semiconductor
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NLV14046BDWG Datasheet PDF : 8 Pages
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Input Stage
X X
PCAin PCBin
PC1out
Input Stage
X X
PCAin PCBin
MC14046B
PHASE COMPARATOR 1
00
11
0
PHASE COMPARATOR 2
01
10
1
00
01
10
11
00
10
01
11
00
01
10
11
PC2out
3−State
0
Output Disconnected
1
LD (Lock Detect)
0
1
0
Refer to Waveforms in Figure 3.
Figure 1. Phase Comparators State Diagrams
Characteristic
Using Phase Comparator 1
Using Phase Comparator 2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ No signal on input PCAin.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Phase angle between PCAin and PCBin.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Locks on harmonics of center frequency.
VCO in PLL system adjusts to center
frequency (f0).
90° at center frequency (f0), approaching
0_ and 180° at ends of lock range (2fL)
Yes
VCO in PLL system adjusts to minimum
frequency (fmin).
Always 0_ in lock (positive rising edges).
No
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Signal input noise rejection.
High
Low
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lock frequency range (2fL).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Capture frequency range (2fC).
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2fL = full VCO frequency range = fmax – fmin.
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Depends on low−pass filter characteristics
(see Figure 3). fC v fL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Center frequency (f0).
The frequency of VCOout, when VCOin = 1/2 VDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VCO output frequency (f).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Note: These equations are intended to be
a design guide. Since calculated component
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ values may be in error by as much as a
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ factor of 4, laboratory experimentation may
be required for fixed designs. Part to part
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ frequency variation with identical passive
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ components is typically less than ± 20%.
1
fmin =
R2(C1 + 32 pF)
1
fmax =
+ fmin
R1(C1 + 32 pF)
Where: 10K v R1 v 1 M
10K v R2 v 1 M
100pF v C1 v .01 mF
(VCO input = VSS)
(VCO input = VDD)
fC = fL
Figure 2. Design Information
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4
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