74AC11PC Просмотр технического описания (PDF) - Fairchild Semiconductor

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74AC11PC

Triple 3-Input AND Gate

Fairchild Semiconductor 

Physical Dimensions

8.75

8.50

7.62

14

6.00

A

8

B

4.00

3.80

0.65

5.60

PIN ONE

INDICATOR

1

1.27

(0.33)

7

0.51

0.35

1.70

1.27

LAND PATTERN RECOMMENDATION

0.25 M C B A

1.75 MAX

1.50

1.25

R0.10

R0.10

8°

0°

SEE DETAIL A

0.25

0.10 C

0.10 C

0.25

0.19

NOTES: UNLESS OTHERWISE SPECIFIED

0.50

0.25

A) THIS PACKAGE CONFORMS TO JEDEC

X 45°

MS-012, VARIATION AB, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

GAGE PLANE FLASH OR BURRS.

D) LANDPATTERN STANDARD:

0.36

SOIC127P600X145-14M

E) DRAWING CONFORMS TO ASME Y14.5M-1994

F) DRAWING FILE NAME: M14AREV13

0.90

0.50

(1.04)

SEATING PLANE

DETAIL A

SCALE: 20:1

Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

©1988 Fairchild Semiconductor Corporation

74AC11 Rev. 1.6.1

5

www.fairchildsemi.com

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