MX128 Просмотр технического описания (PDF) - CML Microsystems Plc
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MX128 Datasheet PDF : 11 Pages
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Audio Band Scrambler
FX/MX128
1.3 Signal List
All
Packages
Signal
Pin No.
1
Name
XTALN
Type
O/P
2
XTAL/CLOCK
I/P
3
-
N/C
4
TXOUT
O/P
5
TX GAIN AMP
OUT
O/P
6
TXIN
I/P
7
-
N/C
8
VSS
Power
9
VBIAS
O/P
10
-
N/C
11
RXIN
I/P
12
RX GAIN AMP
OUT
O/P
13
RXOUT
O/P
14
CLR
I/P
15
CLOCK
SELECT
I/P
16
VDD
Power
Description
This is the output of the clock oscillator inverter.
10.24 MHz, 3.58/3.6864 MHz, or an externally derived clock is
injected at this pin. See Figure 1.
No connection should be made to this pin.
This is the analogue output of the transmit channel. It is internally
biased at VDD/2.
This is the output pin of the transmit channel gain adjusting op-
amp.
See Figure 3 for gain setting components.
This is the analogue signal input to the transmit channel. This
input goes to a gain adjusting op-amp whose gain is set by
external components. See Figure 3.
No connection should be made to this pin.
Negative supply (GND)
This is an internally generated bias voltage output (VDD/2).
It should NOT be decoupled with a capacitor.
No connection should be made to this pin.
This is the analogue signal input to the receive channel. This
input goes to a gain adjusting op-amp whose gain is set by
external components. See Figure 3.
This is the output pin of the receive channel gain adjusting op-
amp. See Figure 3 for gain setting components.
This is the analogue output of the receive channel. It is internally
biased at VDD/2.
A logic 1 on this input selects the invert mode. A logic 0 selects
the clear (not inverted) mode.
Selects either 10.24 or 3.58/3.6864 MHz clock frequency. A logic
“1” selects 10.24 MHz, and a logic “0” selects 3.58/3.6864 MHz.
This input is internally pulled high.
Positive supply of 3.0V to 5.5 V
Notes:
I/P
= Input
O/P = Output
N/C = No Connection
© 2003 CML Microsystems Plc
4
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