IDT9FGV0641 Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT9FGV0641

6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator with Zo=100ohms

Integrated Device Technology 

9FGV0641 DATASHEET

Pin Configuration

40 39 38 37 36 35 34 33 32 31

vSS_EN_tri 1

30 vOE3#

X1_25 2

29 DIF3#

X2 3

28 DIF3

VDDXTAL1.8 4

VDDREF1.8 5

9FGV0641A

27 VDDIO

26 VDDA1.8

vSADR/REF1.8 6

NC 7

Paddle is GND

25 NC

24 vOE2#

GNDDIG 8

23 DIF2#

SCLK_3.3 9

22 DIF2

SDATA_3.3 10

21 vOE1#

11 12 13 14 15 16 17 18 19 20

40-VFQFPN, 5 x 5 mm, 0.4mm pitch

v prefix indicates internal 120kOhm pull-down resistor

^ prefix indicates internal 120kOhm pull-up resistor

SMBus Address Selection Table

State of SADR on first application

of CKPWRGD_PD#

SADR

0

1

Address

1101000

1101010

+ Read/Write Bit

x

x

Power Management Table

CKPWRGD_PD#

SMBus

OE bit

OEx#

DIFx

True O/P

REF

Comp. O/P

0

X

X

Low

Low

Hi-Z1

1

1

0

Running

Running Running

1

0

1

Low

Low

Low

1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when

CKPWRG_PD# is low, REF is Low.

Power Connections

Pin Number

VDD

4

5

VDDIO

11

12,17,27,32,39

26

GND

41

41

8

41

41

Description

XTAL OSC

REF Power

Digital (dirty)

Power

DIF outputs

PLL Analog

6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR WITH ZO=100OHMS

2

JUNE 23, 2017

Share Link: