ISP1583 Просмотр технического описания (PDF) - NXP Semiconductors.
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ISP1583 Datasheet PDF : 100 Pages
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NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
ball A1
index area
A
B
C
D
E
F
G
H
ISP1583ET1
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004aaa991
Transparent top view
Fig 4. Pin configuration ISP1583ET1 (top view)
7.2 Pin description
Table 3. Pin description
Symbol[1] Pin
Type[2] Description
ISP1583BS ISP1583ET; ISP1583ET1
ISP1583ET2
AGND
1
D2
D2
-
analog ground
RPU
2
A1
A1
A
pull-up resistor connection; this pin must be connected to
3.3 V through an external 1.5 kΩ resistor to pull up pin DP
DP
3
B1
B1
A
USB D+ line connection (analog)
DM
4
C1
C1
A
USB D− line connection (analog)
AGND
5
-
-
-
analog ground
RREF
6
D1
D1
A
external bias resistor connection; this pin must be
connected to ground through a 12.0 kΩ ± 1 % resistor
RESET_N 7
E2
C3
I
reset input (500 µs); a LOW level produces an
asynchronous reset; connect to VCC(3V3) for power-on
reset (internal POR circuit)
When the RESET_N pin is LOW, ensure that the WAKEUP
pin does not go from LOW to HIGH; otherwise the device
will enter test mode.
TTL; 5 V tolerant
EOT
8
E1
D3
I
end-of-transfer input (programmable polarity); used in
DMA slave mode only; when not in use, connect this pin to
VCC(I/O) through a 10 kΩ resistor
input pad; TTL; 5 V tolerant
DREQ
9
F2
E1
I/O DMA request input or output (programmable polarity); the
signal direction depends on bit MASTER in register DMA
Hardware (see Table 59):
• Input: DMA master mode if bit MASTER = 1
• Output: DMA slave mode if bit MASTER = 0
When not in use, in the default setting, this pin must be
connected to ground through a 10 kΩ resistor.
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
ISP1583_7
Product data sheet
Rev. 07 — 22 September 2008
© NXP B.V. 2008. All rights reserved.
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