KE5BCCA9M Просмотр технического описания (PDF) - KAWASAKI MICROELECTRONICS

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KE5BCCA9M

high-performance Content Addressable Memory (CAM)

KAWASAKI MICROELECTRONICS 

Kawasaki LSI

9M Classification CAM

PRELIMINARY

4. Functional Descriptions

4.1. Overview

Kawasaki’s KE5BCCA9M has a dual-port architecture: I/O port and Output port. The I/O port is for

search key data input and command input. The search results are output through the Output port.

Commands are asserted through the CNTL[15:0] bus. Read/write of stored data and search key

data are provided through DAT[63:0] and EDAT[7:0]. This 72-bit bus (DAT[63:0] and EDAT[7:0]) can

be defined as 72-bit or 40-bit.

The CAM table consists of 8 banks, each of which can be configured as Ternary and Binary and in

table widths of 72-bit, 144-bit, 288-bit, or 576-bit. The search operation can be performed

simultaneously on multiple banks of the same configuration.

The CAM also has the function called Weighted Search without data sorting. Which is regardless of

the order of the data stored, the most weighted entry is output when a search results in multiple hit.

4.2. Segment Structure

Extra 8bits

Data 64bits

71

64 63

Local Data

Local Mask Data

0

Empty Hit

Bit

Flag

4.3. Output Format

Classification

CAM

OEODN

23 22 21 20

16 15

0

OD[23:0]

DEVID

HHA/HEA[15:0]

SSHON

SMON

Device ID[4:0]

HHA/HEA Flag (0:HHA, 1:HEA)

Valid Flag (0:Valid, 1:Invalid)

HHA[16]/HEA[16]

Version 1.2.0

7

Confidential

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