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W921E843A

4-BIT MICROCONTROLLER

Winbond 

W921E840A/W921C840

The detail function of the system clock control register (SYSCCR) is shown as below:

SYSCCR register: (address = 000H, default data = 0H, only for W921E841A, 843A, 844A)

b3

b2

b1

b0

0: fTM0 = f SYS0

1: fTM0 = f SYS1

0: fH enable

1: fH disable

0: fL enable

1: fL disable

0: fOSC = f 1

1: fOSC = f 2

The W921E840A/W921C840 provides a crystal or RC oscillation circuit selected by bit0 of INI

register (refer to section 6.14) to generate the system clock through external connections. If a crystal

oscillator is used, a crystal or ceramic resonator must be connected to OSCI and OSCO , and the

capacitor is added optionally. The oscillator configuration is shown as follows.

OSCI

or

OSCO

OSCI

OSCO

Crystal Type

RC type

6.4 Initial State

The W921E840A/W921C840 is reset either by a power-on reset or by using the external RESET pin.

The initial state of the W921E840A/W921C840 after the reset function is executed is described

below. The EVF interrupt request signal register value is random, so user must do CLR EVF,

#11111111b instruction to clear all interrupt request signals after power-on reset.

Program counter (PC)

Stack pointer

Special function registers

TM0, TM1, TM2, TM3 input clock

TM0, TM1, TM2, TM3 contents

Input/Output

PM registers

DTMF output

EVF interrupt request signal register

0000H

0FFH

Refer to section 6.2.1

Fosc/8

0FFH

Input mode

1111B

Disable (H-Z)

Random

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