CD4030A Просмотр технического описания (PDF) - Intersil
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CD4030A Datasheet PDF : 2 Pages
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COS/MOS
Quad Exclusive-OR Gate
The RCA-CD4030A types consist of four in-
dependent Exclusive-OR gates integrated on
a single monolithic silicon chip. Each Ex-
clusive-OR gate consists of four n-channel and
four p-channel enhancement-type transistors.
All inputs and outputs are protected against
electrostatic effects.
These types are supplied in 14-lead hermetic
dual-in-line ceramic packages (0 and F
suffixes), 14-lead dual-in-line plastic pack-
age (Esuffix), 14-lead ceramic flat package
(K suffix), and in chip form (H suffix).
CD4030A Typ s
14 VDD
13 H
12 G
II M
10 L
9F
VSS
BE
J'A0B L' E0F
K'C0D M'G0H
MAXIMUM RATINGS, Absolute MaxlfIlum Values
STORAGE TEMPERATURE RANGE IT,,q'
FUNCTIONAL DIAGRAM
OPERATING TEMPERATURE RANGE ITA'
PACKAGE TYPES 0 F H
55 to +125°C Features:
PACKAGE TYPE E
40 to +8SoC • Medium speed operation.
oCSUPPLY·VOLTAGE RANGE IV oo '
(VOltages referenced to VSS Terr""'dll
POWER DISSIPATION PER PACKAGE IPo'
FOR TAe 40to -6QoC (PACKAGE TYPE EI
FOR TA - -60 to -85°C IPACKA~E TYPE E'
FOR T A' 55 to • 100°C IPACKAGE TYPES 0 F I
FOR T A " +100 to "25 0 C IPACKAGE TYPES 0 F I
VICE DISSIPATION PER OUTPUT TRANSISTOR
0 5 to +15 V
. • .tPHL = tPLH = 40 ns (typ.) @ CL = 15 pF
and VDD-VSS = 10 V
• Low output impedance. _ .
~OOmW
n = . . .500 (typ.) @ VDD-VSS 10 V
Derate LInearly at 1'Z mWloC to 'ZOO mW
• Quiescent current specified to 15 V
500 mW
Opr.IIP L"W •• rly.1I 17 rnW °c to 700 mW • Maximum input leakage current of 1 J.l.A
at 15 V (Full package-temperature range)
_
FOR T A' FULL PACKAGE TEMPERATURE RANGE (ALL PACKAGE TYPESi
100 mW • 1-V noise margin (full package-temper-
PUT VOL TAGE RANGE. ALL INPUTS
05 to VoO ·0 S V
ature range)
LEAD TEMPERATURE lOURING SOLDERING'
At d,stance 1/ 16 ! 1132 Inch (1 59 • 0 79 mrn' fr or" c.,,,, lor 10, m ...
Applications:
= RECOMMENDED OPERATING CONDITIONS at TA 250 C,
For maximum reliabIlity, nommal operatmg conditIOns should lJe selected so that
operation IS always wlthm the followmg ranges'
• Even and odd-parity generators
and checkers
• Logical comparators
• Adderslsubtractors
• General logic functions
CHARACTERISTIC
Supply Voltage Range (For TA = Full
Package Temperature Range)
LIMITS
D,F,H
Packages
E
Package
Min. Max. Min. Max.
3 12
3 12
UNITS
V
• 4LL INPUTS ARE
PROTECTED BY
CDS/MDS PROTECTION
NETWORK
TRUTH TABLE FORONEOF
FOUR IDENTICAL GATES
A
BJ
0
00
1
0
1
0
1
1
1
10
WHERE "1" a HIGH LEVEL
"0" " LOW LEVEL
ALL P - CHANNEL suBSTRATES
ARE INTERNALLY CONNECTEO TO VOD
ALL N- CHANNEL SUBSTRATES
ARE INTERNALLY CONNECTED TO VSS
Fig_' - Schematic diagram (or' o( 4 identical exclusive-OR gates.
For quietCllnt device current, noise immunity, end input lakege current test circuits ... "Retinlllend
Cherecteriltics" et the beginning of the COS/MOS lICtion.
DAAIN-TO-$OURCE VOLTS lVos'
Flg.2 - TYPical output n-channel
drain characteristics.
DRAIN-TO-SOURCE VDLTStvos'
Fig.3 - Typical output p-channel
dram characte"stics.
505
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