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UPD78064A Просмотр технического описания (PDF) - NEC => Renesas Technology

Номер в каталоге
Компоненты Описание
Список матч
UPD78064A
NEC
NEC => Renesas Technology NEC
UPD78064A Datasheet PDF : 68 Pages
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µPD78062(A), 78063(A), 78064(A)
5.2 Clock Generator
There are two kinds of clocks, main system clock and subsystem clock.
The minimum instruction execution time can also be changed.
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (main system clock: in 5.0 MHz operation)
122 µs (subsystem clock: in 32.768 kHz operation)
Figure 5-1. Clock Generator Block Diagram
XT1/P07
XT2
X1
X2
Subsystem fXT
Clock
Oscillator
Main
System
Clock
Oscillator
STOP
fX
Selec-
tor
Scaler
fX
2
Prescaler
fXX
1/2
fXX fXX fXX fXX fXT
2 22 23 24 2
Prescaler
Selec-
tor
Standby
Control
Circuit
Watch Timer
Clock Output Function
Clock to
Peripheral
Hardware
CPU
Clock
(fCPU)
To INTP0
Sampling Clock
5.3 Timer/Event Counter
Five timer/event counter channels are incorporated.
16-bit timer/event counter : 1 channel
8-bit timer/event counter : 2 channels
Watch timer
: 1 channel
Watchdog timer
: 1 channel
Table 5-2. Timer/Event Counter Types and Functions
Type
Function
Interval timer
External event counter
Timer output
PWM output
Pulse width measurement
Square wave output
One-shot pulse output
Interrupt request
Test input
16-bit Timer/
Event Counter
1 channel
1 channel
1 output
1 output
2 inputs
1 output
1 output
2
8-bit Timer/
Event Counter
2 channels
2 channels
2 outputs
2 outputs
2
Watch Timer
1 channel
2
1 input
Watchdog Timer
1 channel
1
20

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