HM5264165F-75 Просмотр технического описания (PDF) - Elpida Memory, Inc

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HM5264165F-75

64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5264165F/HM5264805F/HM5264405F-75/A60/B60

Block Diagram (HM5264165F)

Column address

counter

A0 to A7

Column address

buffer

A0 to A13

Row address

buffer

A0 to A13

Refresh

counter

Row decoder

Memory array

Bank 0

4096 row

X 256 column

X 16 bit

Row decoder

Memory array

Bank 1

4096 row

X 256 column

X 16 bit

Row decoder

Memory array

Bank 2

4096 row

X 256 column

X 16 bit

Row decoder

Memory array

Bank 3

4096 row

X 256 column

X 16 bit

Input

buffer

Output

buffer

DQ0 to DQ15

Control logic &

timing generator

Data Sheet E0135H10

6

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