HM5264805F-B60 Просмотр технического описания (PDF) - Elpida Memory, Inc

Номер в каталоге

Компоненты Описание

Список матч

HM5264805F-B60

64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank /4-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM

Elpida Memory, Inc 

HM5264165F/HM5264805F/HM5264405F-75/A60/B60

VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the

output buffer.)

Command Operation

Command Truth Table

The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins.

CKE

Command

Symbol n - 1 n

Ignore command

DESL

H×

No operation

NOP

H×

Burst stop in full page

BST

H×

Column address and read command READ

H×

Read with auto-precharge

READ A H ×

Column address and write command WRIT

H×

Write with auto-precharge

WRIT A H ×

Row address strobe and bank active ACTV

H×

Precharge select bank

PRE

H×

Precharge all bank

PALL

H×

Refresh

REF/SELF H V

Mode register set

MRS

H×

Note: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input

A0

CS RAS CAS WE A12/A13 A10 to A11

H× × × ×

××

L H H H×

××

LHHL×

××

L H L HV

LV

L H L HV

HV

LHL LV

LV

LHL LV

HV

L L H HV

VV

LL HLV

L×

LL HL×

H×

L L L H×

××

LL L LV

VV

Ignore command [DESL]: When this command is set (CS is High), the SDRAM ignore command input at

the clock. However, the internal status is held.

No operation [NOP]: This command is not an execution command. However, the internal operations

continue.

Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page

(256; HM5264165F, 512; HM5264805F, 1024; HM5264405F)), and is illegal otherwise. When data

input/output is completed for a full page of data, it automatically returns to the start address, and input/output

is performed repeatedly.

Data Sheet E0135H10

10

Share Link: