QL5632 Просмотр технического описания (PDF) - QuickLogic Corporation

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Компоненты Описание

производитель

QL5632

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

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Mst_RdData_Valid

Mst_RdBurst_Done

Flush_FIFO

Mst_LatCntEn

Mst_Xfer_D1

Signal

Mst_Last_Cycle

Mst_REQN

Mst_IRDYN

Mst_Tabort_Det

Mst_TTO_Det

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O

Master Read data valid on Usr_Addr_WrData[31:0] This serves as the PUSH control for the

external FIFO (in FPGA region) that receives data from the PCI32 core.

O Master Read transaction is completed Active for only one clock cycle.

I Internal FIFO flush FIFO flushed immediately after it is active (synchronized with PCI clock).

Enable Latency Counter Set to 0 to ignore the Latency Timer in the PCI configuration space

I (offset 0Ch).

For full PCI compliance, this port should be always set to 1.

O

Data was transferred on the previous PCI clock Useful for updating DMA transfer counts on

DMA Read operations

Description

O Active during the last data transfer of a master transaction

O

Copy of the PCI REQN signal generated by QL5632 as PCI master Not usually used in the

back-end design.

O

Copy of the PCI IRDYN signal generated by QL5632 as PCI master Valid only when QL5

× 33 is the PCI master. Kept low otherwise. Not usually used in the back-end design.

O

Target abort detected during master transaction This is normally an error condition to be

handled in the DMA controller.

O

Target timeout detected (no response from target) This is normally an error condition to be

handled in the DMA controller.

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Preliminary

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