QL5632 Просмотр технического описания (PDF) - QuickLogic Corporation

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QL5632

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

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The configuration space is completely customizable in the programmable region of the

device.

PCI address and command decoding is performed by logic in the programmable section of

the device. This allows support for any size of memory or I/O space for back end logic. It

also allows the user to implement any subset of the PCI commands supported by the

QL5632. In the reference design, QuickLogic provides a reference Address

Register/Counter and Command Decode block.

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The customizable DMA controller included with the QuickWorks design software contains

the following features:

‡ Configurable DMA count size for Reads and Writes (up to 30 bits)

‡ Configurable DMA burst size for PCI (including unlimited/continuous burst)

‡ Customizable PCI command to use by core

‡ Customizable Byte Enable signal

‡ Programmable Arbitration between DMA Read & Write transactions

‡ DMA Registers may be mapped to any area of Target Memory Space, including:

‡ Read Address (32-bit register)

‡ Write Address (32-bit register)

‡ Read Length (16-bit register) / Write Length (16-bit register)

‡ Control and Status (32-bit register, includes 8 bit Burst Length)

‡ DMA Registers are available to the local design or the PCI bus

‡ Programmable Interrupt Control to signal end of transfer or other event

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Preliminary

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