QL5632(2003) Просмотр технического описания (PDF) - QuickLogic Corporation

Номер в каталоге

Компоненты Описание

производитель

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

RAM Module Features

The QL6432 device has eighteen 2,304-bit RAM modules, for a total of 41,472 RAM bits. Using

two “mode” pins, designers can configure each module into 128 × 18, 256 × 9, 512 × 4, or 1024

× 2 blocks (see Figure 1). The blocks are also easily cascadable to increase their effective width

or depth.

The RAM modules are “dual-ported” with completely independent Read and Write ports and

separate Read and Write clocks. The Read ports support asynchronous and synchronous

operation, while the Write ports support synchronous operation. Each port has 18 data lines and

10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024 words.

Depending on the mode selected, however, some higher order data or address lines may not be

used.

The Write Enable (WE) line acts as a clock enable for synchronous Write operation. The Read

Enable (RE) acts as a clock enable for synchronous Read operation (ASYNCRD input low), or as

a flow-through enable for asynchronous Read operation (ASYNCRD input high).

Designers can cascade multiple RAM modules to increase the depth or width allowed in single

modules by connecting corresponding address lines together and dividing the words between

modules. This approach allows up to 1,024-deep configurations as large as 44 bits wide in the

QL6432 device.

A similar technique can be used to create depths greater than 1,024 words. In this case, address

signals higher than the eighth bit are encoded onto the write enable (WE) input for Write

operations. The Read data outputs are multiplexed together using encoded higher Read address

bits for the multiplexer SELECT signals.

[9:0]

[17:0]

[1:0]

WA

RE

WD

WE

WCL K

MOD E

RCLK

[9:0]

RA

[17:0]

RD

ASYNCRD

QuickRAM Module

Figure 4: RAM Module

© 2003 QuickLogic Corporation

•

www.quicklogic.com

•

•

11

•

•

•

Share Link: