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LT1175-5

Precision Micropower ∆∑ RMS-to-DC Converter

Linear Technology 

LTC1966

Applications Information

In any configuration, the averaging capacitor should be

connected between Pins 5 and 6. The LTC1966 RMS DC

output will be a positive voltage created at VOUT (Pin 5)

with respect to OUT RTN (Pin 6).

Power Supply Bypassing

The LTC1966 is a switched capacitor device, and large

transient power supply currents will be drawn as the

switching occurs. For reliable operation, standard power

supply bypassing must be included. For single supply

operation, a 0.01µF capacitor from VDD (Pin 7) to GND

(Pin 1) located close to the device will suffice. For dual

supplies, add a second 0.01µF capacitor from VSS (Pin 4)

to GND (Pin 1), located close to the device. If there is a

good quality ground plane available, the capacitors can go

directly to that instead. Power supply bypass capacitors

can, of course, be inexpensive ceramic types.

The sampling clock of the LTC1966 operates at approxi-

mately 200kHz, and most operations repeat at a rate of

100kHz. If this internal clock becomes synchronized to a

multiple or submultiple of the input frequency, significant

conversion error could occur. This is particularly important

when frequencies exceeding 10kHz can be injected into

the LTC1966 via supply or ground bounce. To minimize

this possibility, capacitive bypassing is recommended on

both supplies with capacitors placed immediately adjacent

to the LTC1966. For best results, the bypass capacitors

should be separately routed from Pin 7 to Pin 1, and from

Pin 4 to Pin 1.

The LTC1966 needs at least 2.7V for its power supply,

more for dual supply configurations. The range of allow-

able negative supply voltages (VSS) vs positive supply

voltages (VDD) is shown in Figure 10. Mathematically, the

VSS constraint is:

– 3 • (VDD – 2.7V) ≤ VSS ≤ GND

The LTC1966 has internal ESD absorption devices, which

are referenced to the VDD and VSS supplies. For effective

in-circuit ESD immunity, the VDD and VSS pins must be

connected to a low external impedance. This can be ac-

complished with low impedance power planes or simply

with the recommended 0.01µF decoupling to ground on

each supply.

16

0

–1

–2

LTC1966

OPERATES IN THIS RANGE

–3

–4

–5

–6

2.5 3 3.5 4 4.5

VDD (V)

5 5.5

1966 F10

Figure 10. VSS Limits vs VDD

Up and Running!

If you have followed along this far, you should have the

LTC1966 up and running by now! Don’t forget to enable

the device by grounding Pin 8, or driving it with a logic low.

Keep in mind that the LTC1966 output impedance is fairly

high, and that even the standard 10MΩ input impedance of

a digital multimeter (DMM) or a 10× scope probe will load

down the output enough to degrade its typical gain error

of 0.1%. In the end application circuit, either a buffer or

another component with an extremely high input impedance

(such as a dual slope integrating ADC) should be used.

For laboratory evaluation, it may suffice to use a bench

top DMM with the ability to disconnect the 10MΩ shunt.

If you are still having trouble, it may be helpful to skip

ahead a few pages and review the Troubleshooting Guide.

What About Response Time?

With a large value averaging capacitor, the LTC1966 can

easily perform RMS-to-DC conversion on low frequency

signals. It compares quite favorably in this regard to

prior generation products because nothing about the ∆Σ

circuitry is temperature sensitive. So the RMS result doesn’t

get distorted by signal driven thermal fluctuations like a

log/antilog circuit output does.

However, using large value capacitors results in a slow

response time. Figure 11 shows the rising and falling

step responses with a 1µF averaging capacitor. Although

they both appear at first glance to be standard exponential

1966fb

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