CS5361
SCLK output
LRCK
output
SDOUT
t msl
r
t sd
o
MSB
SCLK input
LRCK input
t sl rd
MSB-1
S DOUT
tsclkh tsclkl
t sclkw
t lrdss
MSB
MSB-1
tdss
MSB-2
Figure 16. Master Mode, Left Justified SAI
Figure 17. Slave Mode, Left Justified SAI
SCLK
output
LRCK output
SDOUT
t mslr
t sdo
MSB
Figure 18. Master Mode, I2S SAI
SCLK input
LRCK input
S DOUT
tsclkh tsclkl
tsclkw
t dss
MSB
MSB-1
Figure 19. Slave Mode, I2S SAI
LRCK
OVFL
t setup
t hold
Figure 20. OVFL Output Timing
19