UT62L6416BS-55LLE Просмотр технического описания (PDF) - Utron Technology Inc

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UT62L6416BS-55LLE

64K X 16 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



UTRON

Preliminary Rev. 1.0

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

Address

DOUT

tAA

tOH

UT62L6416

64K X 16 BIT LOW POWER CMOS SRAM

tRC

tOH

Data Valid

READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)

Address

CE

t RC

t AA

t ACE

OE

LB , UB

Dout

t CLZ

HIGH-Z

t OE

t OLZ

t BLZ

t BA

t CHZ

t OHZ

t BHZ

t OH

Data Valid

HIGH-Z

Notes :

1. WE is HIGH for read cycle.

2. Device is continuously selected CE =VIL.

3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.

4. OE is LOW.

5. tCLZ, tOLZ, tCHZ , tOHZ, tBHZ and tBLZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ. , tBHZ is less than tBLZ.

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

5

P80073

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